1. Field of the Invention
The present invention relates generally to integrated circuit devices and methods of operating the same and, more particularly, to current driver circuits used in an interface circuit and methods of operating the same.
2. Description of the Related Art
A circuit capable of providing a constant current to an output terminal has been widely used in a charge pump included in a PLL (Phase Locked Loop), a digital-to-analog converter (DAC), a current driving interface and the like. An example of such a circuit will be described below.
FIGS. 1A, 1B and 1C are circuit diagrams that illustrate conventional open drain drivers according to three switching types.
Referring to FIGS. 1A, 1B and 1C, in a gate switching type (FIG. 1A), variation of a gate-to-source voltage Vgs of an output NMOS is large. A drain switching type (FIG. 1B) causes a current spike due to a rapid voltage variation between both terminals of a current source. Thus, a source switching type (FIG. 1C) is usually used as the open drain driver.
FIG. 2 illustrates simulation waveforms of the conventional open drain drivers according to the three switching types shown in FIGS. 1A, 1B and 1C.
Referring to FIG. 2, in the gate switching type (represented as ‘G’ in FIG. 2), a current of an output terminal does not follow the variation of an input signal, and the drain switching type (represented as ‘D’ in FIG. 2) causes a current spike as shown in FIG. 2.
In the source switching type (represented as ‘S’ in FIG. 2), a current of an output terminal can follow the variation of the input signal and a current spike doesn't occur.
During on and off operations of the source switching type, an output current has a long rising time and a long falling time because a node between a switch and a current source has a relatively low slew rate; therefore, overall system margin may be decreased.
To prevent the decrease of the overall system margin, there are several modifications of the open drain driver using the source switching type shown in FIG. 1. FIG. 3A is a circuit diagram illustrating a conventional first modified open drain driver. Comparing the open drain driver of FIG. 3A with the source switch type open drain driver of FIG. 1C, the open drain driver shown in FIG. 3A may provide a constant current by maintaining a reference potential ref during switching operations while an input signal din having a logic high level and an input signal din having a logic low level are repeatedly applied.
Referring to FIG. 3A, the open drain driver includes a current source 310, a current supply unit 320, a first pull-down transistor M2, and a second pull-down transistor M6. The current source 310 is coupled between an output terminal OUT and a first node n1, and provides a first reference current based on the reference potential ref, and is implemented using an NMOS transistor M1.
The first pull-down transistor M2 is coupled between the first node n1 and a low power voltage Vss, and performs on and off switching operations in response to the input signal din.
The current supply unit 320 includes a diode coupled PMOS transistor M9 and an NMOS transistor M5. The NMOS transistor M5 corresponds to the NMOS transistor M1, and maintains the reference potential ref during switching operations while the input signal din having a logic high level and the input signal din having a logic low level are repeatedly applied.
The second pull-down transistor M6 corresponds to the first pull-down transistor M2, performs switching operations complementary with respect to the switching operation of the first pull-down transistor M2, and allows the NMOS transistor M1 and the NMOS transistor M5 to operate complementarily with each other. Thus, the reference potential ref may be maintained as a current state.
FIG. 3B is a circuit diagram illustrating a conventional second modified open drain driver. The open drain driver shown in FIG. 3B may address the problem of the open drain driver shown in FIG. 3A. The open drain driver shown in FIG. 3A has the problem that a falling time of a current flowing through the output terminal OUT increases because the NMOS transistor M1 has a turn-on state when the input signal din has a low level until a gate-to-source voltage Vgs of the NMOS transistor M1 becomes less than a threshold voltage Vth of the NMOS transistor M1. The open drain driver shown in FIG. 3B includes an additional pull-up PMOS transistor M4 that quickly pulls up an electric charge of the first node n1 when the input signal din has a logic low level. Thus, the NMOS transistor M1 may be quickly turned-off because a voltage of the first node n1 is quickly pulled-up to a high power voltage VDD when the input signal din has a low level.
Similarly with the open drain driver of FIG. 3A, the open drain driver of FIG. 3B uses a circuit 372 that is coupled to the reference potential ref to reduce variation of the reference potential ref due to switching operations of the input signal din.
FIG. 3C is a circuit diagram illustrating a conventional third modified open drain driver. The open drain driver shown in FIG. 3C uses an NMOS transistor M3 for a pull-up transistor instead of using a PMOS transistor M4 for a pull-up transistor as shown in FIG. 3B.
A voltage of a first node n1 is not pulled-up to the high power voltage VDD but is pulled-up to a voltage of (VDD−Vth). Vth denotes a threshold voltage of an NMOS transistor M3. As a result, a transition speed of the current flowing through the output terminal OUT may increase when a logic level of an input signal is changed to a low state from a high state. Namely, the slew rate of the current flowing through the output terminal OUT may be increased when the input signal changes to a low level from a high level.
Similarly with the open drain driver of FIG. 3B, the open drain driver of FIG. 3C uses a circuit 373 that is coupled to the reference potential ref to minimize variation of the reference potential ref due to switching operations of the input signal din.
FIG. 3D is a circuit diagram illustrating a conventional fourth modified open drain driver. The open drain driver of FIG. 3D uses an operational amplifier to pull up first and second nodes n1, n2 to a reference potential ref, and allows a current source implemented using NMOS transistors M1 and M5 to be quickly turned-off.
The above-described modifications of the open drain driver shown in FIG. 3A through 3D notwithstanding, there remains room for improvement in the art. The open drain driver shown in FIG. 3A has a problem that a falling time of the current at the output terminal OUT is longer, and the open drain driver shown in FIG. 3D includes an operational amplifier so that a relatively large amount of chip area is required, a power consumption increases and a transition speed of the current at the output terminal OUT is relatively low. Namely, the slew rate of the current at the output terminal OUT is relatively low.
The open drain drivers shown in FIGS. 3B and 3C have a problem that a pull-up transistor and a pull-down transistor may be simultaneously turned on. Referring to the open drain driver shown in FIG. 3B, the pull-up transistor M4 implemented using a PMOS transistor has a relatively low mobility compared with that of the NMOS pull-down transistor M2.
Consequently, when a logic state of the input signal din changes to a logic high level from a logic low level, a large amount of current may flow to the ground during the on/off transition because the pull-up transistor M4 isn't turned-off even after the pull-down transistor M2 is turned-on, i.e. the pull-up transistor M4 and the pull-down transistor M2 are simultaneously turned on.
In the open drain driver shown in FIG. 3C, both the pull-up transistor M3 and the pull-down transistor M2 are implemented using an NMOS transistor, however, each of the NMOS transistors M3 and M2 may have a different transition speed from each other. When a transition speed of the pull-up transistor M3 is slower than that of the pull-down transistor M2, the same problem as that of FIG. 3B may occur.
In case that a transition speed of the pull-up transistor M3 is faster than that of the pull-down transistor M2, when a logic state of the input signal din changes to a logic low level from a logic high level, a relatively large amount of current may flow to ground during the on/off transition because the pull-up transistor M3 is turned-off while the pull-down transistor M2 is not yet turned-on, i.e. the pull-up transistor M3 and the pull-down transistor M2 are simultaneously turned on.
As a result, a short current path between the high power voltage VDD and the low power voltage Vss is generated and a current flowing through the short current path brings a substrate noise and power consumption may increase.